M16C62_M Datasheet, PDF (392/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

UART
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Transfer rate
The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans-
fer rate. The count source for the transfer rate register can be selected from f1, f8, f32, and the input
from the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU’s main clock by 1, 8, and 32
respectively.
Table 2.5.2. Example of baud rate setting
Baud rate
(bps)
BRG's
count source
System clock : 16MHz
BRG's set value : n Actual time (bps)
600
f8
207 (CF16)
601
1200
f8
103 (6716)
1202
2400
f8
51 (3316)
2404
4800
f1
207 (CF16)
4808
9600
f1
103 (6716)
9615
14400
f1
68 (4416)
14493
19200
f1
51 (3316)
19231
28800
f1
34 (2216)
28571
31250
f1
33 (2116)
31250
System clock : 7.3728MHz
BRG's set value : n Actual time (bps)
95 (5F16)
600
47 (2F16)
1200
23 (1716)
2400
95 (5F16)
4800
47 (2F16)
9600
31 (1F16)
14400
23 (1716)
19200
15 (F16)
28800
(3) An error detection
In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.5.3.
Table 2.5.3. Error detection
Type of error
Description
When the flag turns on
How to clear the flag
Overrun error
Framing error
Parity error
Error-sum flag
• This error occurs when the
next data lines up before the
content of the UARTi receive
buffer register is read.
• The next data is written to the
UARTi receive buffer register.
• The UARTi receive interrupt
request bit does not change.
• This error occurs when the
stop bit falls short of the set
number of stop bits.
• With parity enabled, this error
occurs when the total number
of 1's in character bits and the
parity bit is different from the
specified number.
• This flag turns on when any
error (overrun, framing, or
parity) is detected.
• Set the serial I/O mode select
bits to “0002”.
• Set the receive enable bit to
“0”.
The error is detected
when data is
• Set the serial I/O mode select
transferred from the
bits to ”0002”.
UARTi receive register ^{• Set the receive enable bit to}
to the UARTi receive ^{“0”.}
buffer register.
• Read the lower-order byte of
the UARTi receive buffer
register.
• When all error (overrun,
framing, and parity) are
removed, the flag is cleared.
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