M16C62_M Datasheet, PDF (493/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Power Control
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Sequence of returning from stop mode
Sequence of returning from stop mode is oscillation start-up time and interrupt sequence.
When interrupt is generated in stop mode, CM10 becomes “0” and clearing stop mode.
Starting oscillation and supplying BCLK execute the interrupt sequence as follow:
In the interrupt sequence, the processor carries out the following in sequence given:
(a) CPU gets the interrupt information (the interrupt number and interrupt request level) by read-
ing address 0000016. The interrupt request bit of the interrupt written in address 0000016 will
then be set to “0”.
(b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignment
flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software
interrupt numbers 32 through 63, is executed)
(d) Saves the content of the temporary register (Note) within the CPU in the stack area.
(e) Saves the content of the program counter (PC) in the stack area.
(f) Sets the interrupt priority level of the accepted instruction in the IPL.
Note: This register cannot be utilized by the user.
After the interrupt sequence is completed, the processor resumes executing instruc-
tions from the first address of the interrupt routine.
Figure 2.15.2 shows the sequence of returning from stop mode.
Writing “1” to CM10
(all clock stop control bit)
Operated by divided-by-8 mode
BCLK
Address bus
Data bus
RD
WR
INTi
Address
00000
Indeterminate
Interrupt
information
Indeterminate
Indeterminate
SP-2 SP-4 vec vec+2 PC
SP-2 SP-4
vec
vec+2
contents contents contents contents
Stop mode Oscillation start-up
Interrupt sequence approximately 20 cycle (13µ sec)
(Single-chip mode, f(XIN) = 16MHz)
Note: Shown above is the case where the main clock is selected for BCLK. If the sub-clock is selected for BCLK,
the sub-clock functions as BCLK when restored from stop mode, with the main clock's divide ratio
unchanged.
Figure 2.15.2. Sequence of returning from stop mode
(6) Registers related to power control
Figure 2.15.3 shows the memory map of power control-related registers, and Figure 2.15.4 shows
power control-related registers.
000616 System clock control register 0 (CM0)
000716 System clock control register 1 (CM1)
Figure 2.15.3. Memory map of power control-related registers
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