M16C62_M Datasheet, PDF (531/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Controlling Power Applications
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Initial condition
b7
1
b0 Pull-up control register 2
[Address 03FE16]
PUR2
P104 to P107 pulled high
b7
b0 Port P10 register
0 0 0 0 ^{[Address 03F416]}
P10
Key scan data
Main
b7
b0 Port P10 direction register
0 0 0 0 1 1 1 1 ^{[Address 03F616]}
PD10
Key scan output port
Key scan input port
b7
b0 ^{Key input interrupt control register}
00 1
[Address 004D16]
KUPIC
Interrupt priority level select bit
Set higher value than the present IPL
Processor interrupt priority level (IPL) = 0
Interrupt enable flag (I) =0
Setting interrupt except stop mode cancel
Interrupt control register TBiIC(i=3 to 5) [Address 004516 to 004716]
BCNIC
[Address 004A16]
DMiIC(i=0, 1) [Address 004B16, 004C16]
ADIC
[Address 004E16]
SiTIC(i=0 to 2) [Address 005116, 005316, 004F16]
SiRIC(i=0 to 2) [Address 005216, 005416, 005016]
b7
b0 TAiIC(i=0 to 4) [Address 005516 to 005916]
b7
0 0 0 TBiIC(i=0 to 2) [Address 005A16 to 005C16]
0
Interrupt priority level select bit
000 : Interrupt disabled
Canceling protect
b7
b0 _{Protect register [Address 000A16]}
1 _PRCR
Enables writing to system clock control registers 0 and 1
(addresses 000616 and 000716)
1 : Write-enabled
b0
0 0 0 INTiIC(i=0 to 2) [Address 005D16 to 005F16]
Interrupt priority level select bit
000 : Interrupt disabled
Reserved bit
Must always be set to “0”
Setting operation clock after returning from stop mode
(When operating with XIN after returning)
b7
0
0
System clock control register 0
b0
[Address 000616]
CM0
Main clock (XIN-XOUT) stop bit
On
System clock select bit
XIN, XOUT
As this register becomes setting mentioned above when
operating with XIN (count source of BCLK is XIN),
the user does not need to set it again.
(When operating with XCIN after returning)
b7
1
1
System clock control register 0
b0
[Address 000616]
CM0
Port XC select bit
XCIN-XCOUT generation
System clock select bit
XCIN, XCOUT
As this register becomes setting mentioned above when operating with XCIN
(count source of BCLK is XCIN), the user does not need to set it again.
When operating with XIN, set port Xc select bit to “1” before setting system
clock select bit to “1”. The both bits cannot be set at the same time.
Interrupt enable flag (I flag) “1”
All clocks off (stop mode)
b7
b0
0 0 0 0 1 ^{System clock control register 1 [Address 000716]}
CM1
All clock stop control bit
1 : All clocks off (stop mode)
Reserved bit
Must always be set to “0”
NOP instruction X 4
Key input interrupt request generation
Figure 3.7.3. Set-up procedure of controlling power using stop mode (1)
2-214