M16C62_M Datasheet, PDF (487/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Multiple Interrupts
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(6) Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the
highest priority level. Figure 2.14.5 shows the circuit that judges the interrupt priority level.
Priority level of each interrupt
INT1
Timer B2
Level 0 (initial value)
Timer B0
Timer A3
Timer A1
Timer B4
INT3
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer B3
Timer B5
UART1 reception
UART0 reception
UART2 reception/ACK
A-D conversion
DMA1
Bus collision detection
Serial I/O4/INT5
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission/NACK
Key input interrupt
DMA0
Serial I/O3/INT4
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Address match
Watchdog timer
DBC
NMI
Reset
High
Priority of peripheral I/O interrupts
(if priority levels are same)
Low
Interrupt request level judgment output
to clock generating circuit (Fig.1.10.3)
Interrupt
request
accepted
Figure 2.14.5. Interrupts resolution circuit
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