M16C62_M Datasheet, PDF (465/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

DMAC
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.9.2 Operation of DMAC (one-shot transfer mode)
In one-shot transfer mode, choose functions from the items shown in Table 2.9.1. Operations of the
circled items are described below. Figure 2.9.4 shows an example of operation and Figure 2.9.5
shows the set-up procedure.
Table 2.9.1. Choosed functions
Item
Set-up
Transfer space
O Fixed address from an arbitrary 1 M bytes space
Arbitrary 1 M bytes space from a fixed address
Fixed address from fixed address
Unit of transfer
O 8 bits
16 bits
Operation _{(1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA}
transfer request signal.
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
forward-direction address pointer are transferred to the address indicated by the DMAi desti-
nation pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 1 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
(3) If the DMA transfer counter underflows, the DMA enable bit changes to “0” and DMA transfer
is completed. The DMA interrupt request bit changes to “1” simultaneously.
BCLK
Address bus
RD signal
WR signal
Data bus
Write signal to
software DMAi
request bit
DMAi
request bit
DMA transfer
counter
DMAi
interrupt
request bit
DMAi
enable bit
(1) Request signal for a DMA transfer occurs
(2) Data transfer begins
CPU use
Destination
Source
Dummy
cycle
CPU use
Destination
Source
Dummy
cycle
Indeterminate
0116
• In the case in which the number of transfer times is set to 2.
CPU use
CPU use
0016
Figure 2.9.4. Example of operation of one-shot transfer mode
2-148
(3) Underflow
Destination
Source
Dummy
cycle
CPU use
Destination
Source
Dummy
cycle
CPU use
FF16
Cleared to “0” when interrupt request is
accepted, or cleared by software