M16C62_M Datasheet, PDF (525/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

DMAC Applications
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.6 Memory to Memory DMA Transfer
Overview The following are steps for changing both source address and destination address to transfer
data from memory to another. The DMA transfer utilizes the workings that assign a higher priority
to the DMA0 transfer if transfer requests simultaneously occur in two DMA channels. Figure
3.6.1 shows the operation timing, Figure 3.6.2 shows the block diagram, and Figures 3.6.3 and
3.6.4 show the set-up procedure.
Use the following peripheral functions:
• Timer mode of timer A
• Two DMAC channels
• One-byte temporary RAM (address 080016)
Specifications
(1) Transfer the content of memory extending over 128 bytes from address A000016 to a 128-
byte area starting from address C000016. Transfer the content every time a timer A0 interrupt
request occurs.
(2) Use DMA0 for a transfer from the source to built-in memory, and DMA1 for a transfer from
built-in memory to the destination.
Operation (1) A timer A interrupt request occurs. Though both a DMA0 transfer request and a DMA1 trans-
fer request occur simultaneously, the former is executed first.
(2) DMA0 receives a transfer request and transfers data from the source to the built-in memory.
At this time, the source address is incremented.
(3) Next, DMA1 receives a transfer request and transfers data involved from built-in memory to
the destination. At this time, the destination address is incremented.
Timer A0
“1”
transfer request “0”
Address bus
“1”
RD signal
“0”
(1) Transfer request generation
(3) Start DMA1 transferring
(2) Start DMA0 transferring
Source address
Source address
A000016
080016
080016
C000016
Destination address
Destination address
WR signal
“1”
“0”
Instruction cycle
DMA0 operation
DMA1 operation
Note 1: The DMA0 operation and DMA1 operation are not necessarily executed in succession
due to the a cycle steal operation.
Note 2: The instruction cycle varies from instruction to instruction.
Note 3: Since the parts of the RD and WR signals shown in short-dash lines vary in step with
writing to the internal RAM, waveforms are not output to the RD and WR pins.
Figure 3.6.1. Operation timing of memory to memory DMA transfer
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