M16C62_M Datasheet, PDF (450/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

A-D Converter
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.11 Method of A-D Conversion (10-bit mode)
(1) The A-D converter compares the reference voltage (Vref) generated internally based on the
contents of the successive comparison register with the analog input voltage (VIN) input from
the analog input pin. Each bit of the comparison result is stored in the successive comparison
register until analog-to-digital conversion (successive comparison method) is complete. If a
trigger occurs, the A-D converter carries out the following:
1. Fixes bit 9 of the successive comparison register.
Compares Vref with VIN: [In this instance, the contents of the successive comparison
register are “10000000002” (default).]
Bit 9 of the successive comparison register varies depending on the comparison re-
sult as follows.
If Vref < VIN, then “1” is assigned to bit 9.
If Vref > VIN, then “0” is assigned to bit 9.
2. Fixes bit 8 of the successive comparison register.
Sets bit 8 of the successive comparison register to “1”, then compares Vref with VIN.
Bit 8 of the successive comparison register varies depending on the comparison
result as follows:
If Vref < VIN, then “1” is assigned to bit 8.
If Vref > VIN, then “0” is assigned to bit 8.
3. Fixes bit 7 through bit 0 of the successive comparison register.
Carries out step 2 above on bit 7 through bit 0.
After bit 0 is fixed, the contents of the successive comparison register (conversion
result) are transmitted to A-D register i.
Vref is generated based on the latest content of the successive comparison register. Table
2.7.10 shows the relationship of the successive comparison register contents and Vref. Table
2.7.11 shows how the successive comparison register and Vref vary while A-D conversion is
in progress. Figure 2.7.23 shows theoretical A-D conversion characteristics.
Table 2.7.10. Relationship of the successive comparison register contents and Vref
Successive approximation register : n
Vref (V)
0
1 to1023
VREF
1024
0
x n–
VREF
2048
2-133