M16C62_M Datasheet, PDF (214/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Timing (Vcc = 3V)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20^oC to 85^oC / – 40^oC to
85^oC (Note 2), CM15=“1” unless otherwise specified)
Table 1.23.39. Memory expansion and microprocessor modes
(when accessing external memory area with wait, and select multiplexed bus)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
td(AD-RD)
td(AD-WR)
tdZ(RD-AD)
Parameter
Standard
Measuring condition
Min. Max.
Address output delay time
Address output hold time (BCLK standard)
60
4
Address output hold time (RD standard)
Address output hold time (WR standard)
(Note1)
(Note1)
Chip select output delay time
Chip select output hold time (BCLK standard)
60
4
Chip select output hold time (RD standard)
(Note1)
Chip select output hold time (WR standard)
RD signal output delay time
(Note1)
60
RD signal output hold time
WR signal output delay time
Figure 1.23.7 ⁰
60
WR signal output hold time
Data output delay time (BCLK standard)
0
80
Data output hold time (BCLK standard)
4
Data output delay time (WR standard)
Data output hold time (WR standard)
(Note1)
(Note1)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
60
–4
ALE signal output delay time (Address standard)
ALE signal output hold time(Address standard)
(Note1)
50
Post-address RD signal output delay time
0
Post-address WR signal output delay time
Address output floating start time
0
8
Note: Calculated according to the BCLK frequency as follows:
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 ⁹
th(RD – AD) =
f(BCLK) X 2
[ns]
10 ⁹
th(WR – AD) =
f(BCLK) X 2
[ns]
10 ⁹
th(RD – CS) =
f(BCLK) X 2
[ns]
10 ⁹
th(WR – CS) =
f(BCLK) X 2
[ns]
td(DB – WR) =
10 ⁹ X 3 _{– 80}
f(BCLK) X 2
[ns]
10 ⁹
th(WR – DB) =
f(BCLK) X 2
[ns]
10 ⁹
td(AD – ALE) = _{f(BCLK) X 2 – 45 [ns]}
Note 2: Specify a product of -40°C to 85°C to use it.
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