M16C62_M Datasheet, PDF (558/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

External Buses
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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4.5 Releasing an External Bus (HOLD input and HLDA output)
The Hold feature is to relinquish the address bus, the data bus, and the control bus on M16C/62A side in
line with the Hold request from the bus master other than M16C/62A when the two or more bus masters
share the address bus, the data bus, and the control bus. The Hold feature is effective only in memory
expansion mode and microprocessor mode.
The sequence of using the Hold feature may be:
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1. The external bus master turns the input level of the HOLD terminal to “L”.
2. When M16C/62A becomes ready to relinquish buses, each bus becomes high-impedance state at the
falling edge of BCLK.
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3. The HLDA terminal becomes “L” at the rising edge of the next BCLK.
4. The external bus master uses a bus.
5. When the external bus master finishes using a bus, the external bus master returns the input level of
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the HOLD terminal to “H”.
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6. The output from HLDA terminal becomes “H” at the rising edge of the next BCLK.
7. Each bus returns from the high-impedance state to the former state at the falling edge of the next
BCLK.
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As given above, each bus invariably gets in the high-impedance state while the HLDA output is “L”. Also,
M16C/62A does not relinquish buses during a bus cycle. That is, if a Hold request comes in during a bus
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cycle, the HLDA output become “L” after that bus cycle finishes.
In the Hold state, the state of each terminal becomes as follows.
• Address bus A0 to A19
High-impedance state. The case in which A16 to A19 are used as ports P40 to P43 (64K byte address
space) and the case in which A9 to A19 are used as ports P31 to P37 and P40 to P43 (multiplex for the
whole area) in microprocessor mode and in memory expansion mode too fall under this category.
• Data bus D0 to D15
High-impedance state. The case in which D8 to D15 are used as ports P10 to P17 (8-bit external bus
width) and the case in which D0 to D15 are used as ports P00 to P07 and P10 to P17 (multiplex for the
whole area) in microprocessor mode and in memory expansion mode too fall under this category.
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• RD, WR, WRL, WRH, BHE
High-impedance state.
• ALE
An internal clock signal having the same phase as BCLK is output.
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• CS0 to CS3
High-impedance state. The case in which ports are selected by the chip selection control register too
falls under this category.
Figure. 4.5.1 shows an example of relinquishing external buses.
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