HD6473258CP10 Datasheet, PDF (95/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Input Latches: All pins of port 3 have input latches which can be enabled by the LTE bit in the
handshake control/status register (HCSR) in mode 3. When the LTE bit is set to 1, input data are
latched on the falling edge of the input strobe (IS) signal and held in the input strobe latch until
read. When the LTE bit is cleared to 0, input data are passed through the input strobe latch without
being held.
See section 6, Parallel Handshaking Interface for further information.
Reset and Hardware Standby Mode: P3DDR and P3DR are cleared to all 0, and all parallel
handshaking functions are disabled. All pins are placed in the input (high-impedance) state with the
MOS pull-ups off.
Software Standby Mode: P3DDR and P3DR remain in their previous state. In modes 1 and 2, all
pins are placed in the input (high-impedance) state. In mode 3, all pins remain in their previous
input or output state.
Figure 5-3 shows a schematic diagram of port 3.
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