HD6473258CP10 Datasheet, PDF (49/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.5.2 Arithmetic Operations
Table 3-3 describes the arithmetic instructions. See figure 3-6 in section 3.5.4, “Shift Operations”
for their object codes.
Table 3-3. Arithmetic Instructions
Instruction
ADD
SUB
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
MULXU
DIVXU
CMP
NEG
Size*
B/W
B
B
W
B
B
B
B/W
B
Function
Rd ± Rs → Rd, Rd + #imm → Rd
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data can
be added or subtracted only when both words are in general registers.
Rd ± Rs ± C → Rd, Rd ± #imm ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data and
data in a general register.
Rd ± #1 → Rd
Increments or decrements a general register.
Rd ± #imm → Rd
Adds or subtracts immediate data to or from data in a general register.
The immediate data must be 1 or 2.
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR.
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
Rd – Rs, Rd – #imm
Compares data in a general register with data in another general register
or with immediate data. Word data can be compared only between two
general registers.
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register.
* Size: operand size
B: Byte
W: Word
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