HD6473258CP10 Datasheet, PDF (60/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.5.7 System Control Instructions
Table 3-8 describes the system control instructions. Figure 3-9 shows their object code formats.
Table 3-8. System Control Instructions
Instruction
RTE
SLEEP
LDC
STC
ANDC
ORC
XORC
NOP
Size Function
— Returns from an exception-handling routine.
— Causes a transition to the power-down state.
B
Rs → CCR, #imm → CCR
Moves immediate data or general register contents to the condition code
register.
B
CCR → Rd
Copies the condition code register to a specified general register.
B
CCR ∧ #imm → CCR
Logically ANDs the condition code register with immediate data.
B
CCR ∨ #imm → CCR
Logically ORs the condition code register with immediate data.
B
CCR ⊕ #imm → CCR
Logically exclusive-ORs the condition code register with immediate
data.
— PC + 2 → PC
Only increments the program counter.
* Size: operand size
B: Byte
51