HD6473258CP10 Datasheet, PDF (61/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

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Op
0
RTE, SLEEP, NOP
Op
r_n
LDC, STC (Rn)
Op
Notation
Op:
rn:
#imm.:
Operation field
Register field
Immediate data
#imm.
ANDC, ORC, XORC, LDC
(#xx:8)
Figure 3-9. System Control Instruction Codes
3.5.8 Block Data Transfer Instruction
Table 3-9 describes the EEPMOV instruction. Figure 3-10 shows its object code format.
Table 3-9. Block Data Transfer Instruction/EEPROM Write Operation
Instruction
EEPMOV
Size Function
— if R4L ≠ 0 then
repeat @R5+ → @R6+
R4L – 1 → R4L
until R4L = 0
else next;
Moves a data block according to parameters set in general registers R4L,
R5, and R6.
R4L: size of block (bytes)
R5: starting source address
R6: starting destination address
Execution of the next instruction starts as soon as the block transfer is
completed.
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