HD6473258CP10 Datasheet, PDF (27/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

External memory is accessed a byte at a time in three or more states. The basic bus cycle is three
states, but additional wait states can be inserted on request.
2.3.2 IOS
There are two gaps in the on-chip address space above the on-chip RAM. Addresses H’FF80 to
H’FF8F, situated between the on-chip RAM and register field, are off-chip. Addresses H’FFA0 to
H’FFAF are also off-chip. These 32 addresses can be conveniently assigned to external I/O devices.
To simplify the addressing of devices at these addresses, an IOS signal is provided that goes low
when the CPU accesses addresses H’FF00 to H’FFFF. The IOS signal can be used in place of the
upper 8 bits of the address bus.
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