HD6473258CP10 Datasheet, PDF (135/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

In addition, if the output enable bit (OEA or OEB) in the timer output compare control register
(TCR) is set to 1, when the output compare register and FRC values match, the logic level selected
by the output level bit (OLVLA or OLVLB) in the TCSR is output at the output compare pin
(FTOA or FTOB).
Because OCRA and OCRB are 16-bit registers, a temporary register (TEMP) is used for write
access, as explained in section 7.3, CPU Interface.
OCRA and OCRB are initialized to H’FFFF at a reset and in the standby modes.
7.2.3 Input Capture Register (ICR) – H’FF98
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial 0 0 0
value
Read/ R R R
Write
0 00 0 0 0 0 0 0
R RR R R R R R R
000 0
RRR R
The input capture register is a 16-bit read-only register.
When the rising or falling edge of the signal at the input capture pin (FTI) is detected, the current
value of the FRC is copied to the input capture register (ICR). At the same time, the input capture
flag (ICF) in the timer control/status register (TCSR) is set to 1. The input capture edge is selected
by the input edge select bit (IEDG) in the TCSR.
Because the input capture register is a 16-bit register, a temporary register (TEMP) is used when it
is read. See Section 7.3, CPU Interface for details.
To ensure input capture, when the noise canceler is not used, the width of the input capture pulse
(FTI) should be at least 1.5 system clock cycles (1.5·Ø).
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