HD6473258CP10 Datasheet, PDF (167/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Accordingly, when the timer count matches one of the time constants, the compare-match signal is
not generated until the next period of the clock source. Figure 8-5 shows the timing of the setting
of the compare-match flags.
Øf
TCNT
N
N+1
TCOR
N
Internal
compare-match
signal
CMF
Figure 8-5. Setting of Compare-Match Flags
(2) Timing of Compare-Match Flag (CMFA or CMFB) Clearing: The compare-match flag
CMFA or CMFB is cleared when the CPU writes a 0 in this bit.
Write cycle: CPU writes 0 in CMFA or CMFB
T1
T2
T3
Ø
CMFA
or CMFB
Figure 8-6. Clearing of Compare-Match Flags
(3) Output Timing: When a compare-match event occurs, the timer output (TMO0 or TMO1)
changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits,
the output can remain the same, change to 0, change to 1, or toggle. If compare-match A and B
occur simultaneously, the higher priority compare-match determines the output level. See item (4)
in section 8.6, Application Notes for details.
Fig 8-6
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