HD6473258CP10 Datasheet, PDF (195/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

If a receive error occurs, the RDRF bit in the SSR is not set to 1. (For an overrun error, RDRF is
already set to 1.) The corresponding error flag is set to 1 instead. If the RIE bit in the SCR is set to
1, a receive-error interrupt (ERI) is requested.
When a framing or parity error occurs, the RSR contents are transferred to the RDR. If an overrun
error occurs, however, the RSR contents are not transferred to the RDR.
If multiple receive errors occur simultaneously, all the corresponding error flags are set to 1.
To clear a receive-error flag (ORER, FER, or PER), software must read the SSR and then write a 0
in the flag bit.
Table 9-8. Receive Errors
Name
Overrun error
Abbreviation
ORER
Framing error
FER
Parity error
PER
Description
Reception of the next frame ends while the
RDRF bit is still set to 1.
The RSR contents are not transferred to the
RDR.
A stop bit is 0.
The RSR contents are transferred to the RDR.
The parity of a frame does not match the value
selected by the O/E bit in the SMR.
The RSR contents are transferred to the RDR.
9.3.3 Synchronous Mode
The synchronous mode is suited for high-speed, continuous data transfer. Each bit of data is
synchronized with a serial clock pulse at the SCK pin.
Continuous data transfer is enabled by the double buffering employed in both the transmit and
receive sections of the SCI. Full duplex communication is possible because the transmit and
receive sections are independent.
(1) Data Format: Figure 9-4 shows the communication format used in the synchronous mode.
The data length is 8 bits for both the transmit and receive directions. The least significant bit (LSB)
is sent and received first. Each bit of transmit data is output from the falling edge of the serial
clock pulse to the next falling edge. Received bits are latched on the rising edge of the serial clock
pulse.
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