HD6473258CP10 Datasheet, PDF (153/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

7.8 Application Notes
Application programmers should note that the following types of contention can occur in the free-
running timer.
(1) Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the T3 state of a write cycle to the lower byte of the free-running counter, the clear signal
takes priority and the write is not performed.
Figure 7-17 shows this type of contention.
FRC lower byte write cycle
T1
T2
T3
Ø
Internal address bus
Internal write signal
FRC address
FRC clear signal
FRC
N
H'0000
Figure 7-17. FRC Write-Clear Contention
(2) Contention between FRC Write and Increment: If an FRC increment pulse is generated
during the T3 state of a write cycle to the lower byte of the free-running counter, the write takes
priority and the FRC is not incremented.
Figure 7-18 shows this type of contention.
Fig 7-17
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