HD6473258CP10 Datasheet, PDF (75/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 4-3. Registers Read by Interrupt Controller
Name
System control register
IRQ sense control register
IRQ enable register
Abbreviation
SYSCR
ISCR
IER
Read/Write
R/W
R/W
R/W
Address
H’FFC4
H’FFC6
H’FFC7
(1) System Control Register (SYSCR)—H’FFC4
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
2
1
— NMIEG —
1
0
1
— R/W —
0
RAME
1
R/W
Bit 2 (NMIEG) is the only bit read by the interrupt controller.
Bit 2—Nonmaskable Interrupt Edge (NMIEG): Determines whether a nonmaskable interrupt is
generated on the falling or rising edge of the NMI input signal.
Bit 2
NMIEG
0
1
Description
An interrupt is generated on the falling edge of NMI.
An interrupt is generated on the rising edge of NMI.
(Initial state)
See section 10, RAM and section 12, Power-Down State for information on the other SYSCR bits.
(2) IRQ Sense Control Register (ISCR)—H’FFC6
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
— IRQ2EG IRQ1EG IRQ0EG — IRQ2SC IRQ1SC IRQ0SC
1
0
0
0
1
0
0
0
—
R/W R/W R/W
—
R/W R/W R/W
Bits 6 and 2—IRQ2 Sense Control (IRQ2SC and IRQ2EG): These bits select how the input at
the IRQ2 pin is sensed.
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