HD6473258CP10 Datasheet, PDF (35/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

2.4.2 System Control Register (SYSCR)—H’FFC4
By setting or clearing bit 0 of the system control register, software can enable or disable the on-chip
RAM.
The other bits in the system control register concern the software standby mode and the valid edge
of the NMI signal. These bits will be described in section 4, Exception Handling and section 12,
Power-Down State.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
2
1
0
— NMIEG — RAME
1
0
1
1
—
R/W
—
R/W
Bit 0—RAM Enable (RAME): This bit enables or disables the on-chip RAM. When the on-chip
RAM is disabled, accesses to the corresponding addresses are directed off-chip.
The RAME bit is initialized to 1 by a reset, enabling the on-chip RAM. The setting of the RAME
bit is not altered in the sleep mode or software standby mode. It should be cleared to 0 before
entering the hardware standby mode. See section 12, Power-Down State.
Bit 0
RAME
0
1
Description
The on-chip RAM is disabled.
The on-chip RAM is enabled.
(Initial state)
Coding Example: To disable the on-chip RAM:
BCLR #0, @H’FFC4
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