HD6473258CP10 Datasheet, PDF (79/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Note: Interrupt requests are not detected immediately after the ANDC, ORC, XORC, and LDC
instructions.
4.3.5 Interrupt Handling
Figure 4-3 shows a block diagram of the interrupt controller. Figure 4-4 is a flowchart showing the
operation of the interrupt controller and the sequence by which an interrupt is accepted. This
sequence is outlined below.
(1) The interrupt controller receives an interrupt request signal. Interrupt request signals can be
generated by NMI input, or by other interrupt sources if enabled.
(2) When notified of an interrupt, the interrupt controller scans the interrupt signals in priority
order and selects the one with the highest priority. (See table 4-2 for the priority order.) Other
requested interrupts remain pending.
(3) The interrupt controller accepts the interrupt if it is an NMI, or if it is another interrupt and the
I bit in the CCR is cleared to 0. If the interrupt is not an NMI and the I bit is set to 1, the
interrupt is held pending.
(4) When an interrupt is accepted, after completion of the current instruction, first the PC then the
CCR is pushed onto the stack. See figure 4-5. The stacked PC indicates the address of first
instruction executed after return from the interrupt-handling routine.
(5) The interrupt controller sets the I bit in the CCR to 1, masking all further interrupts except
NMI during the interrupt-handling routine.
(6) The interrupt controller generates the vector address of the interrupt and loads the word at this
address into the program counter.
70