HD6473258CP10 Datasheet, PDF (198/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

ΠSet up the desired receiving conditions in the SMR, BRR, and SCR.
 Set the RE bit in the SCR to 1.
The RxD pin is automatically be switched to input and the SCI is ready to receive data.
Ž Incoming data bits are latched in the RSR on eight clock pulses.
When 8 bits of data have been received, the SCI sets the RDRF bit in the SSR to 1. If the RIE
bit is set to 1, a receive-end interrupt (RXI) is requested.
 The SCI transfers the received data byte from the RSR to the RDR so that it can be read.
The RDRF bit is cleared when software reads the RDRF bit in the SSR, then writes a 0 in the
RDRF bit.
The RDR and RSR function as a double buffer. Data can be received continuously by reading each
byte of data from the RDR and clearing the RDRF bit to 0 before the last bit of the next byte is
received.
In general, an external clock source should be used for receiving data.
If an internal clock source is selected, the SCI starts receiving data as soon as the RE bit is set to 1.
The serial clock is also output at the SCK pin. The SCI continues receiving until the RE bit is
cleared to 0.
If the last bit of the next data byte is received while the RDRF bit is still set to 1, an overrun error
occurs and the ORER bit is set to 1. If the RIE bit is set to 1, a receive-error interrupt (ERI) is
requested. The data received in the RSR are not transferred to the RDR when an overrun error
occurs.
After an overrun error, reception of the next data is enabled when the ORER bit is cleared to 0.
• Simultaneous Transmit and Receive: The procedure for transmitting and receiving
simultaneously is as follows:
ΠSet up the desired communication conditions in the SMR, BRR, and SCR.
 Set the TE and RE bits in the SCR to 1.
The TxD and RxD pins are automatically switched to output and input, respectively, and the
SCI is ready to transmit and receive data.
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