HD6473258CP10 Datasheet, PDF (136/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

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FTIA, FTIB,
FTIC, or FTID
Figure 7-2. Minimum Input Capture Pulse Width (Noise Canceler Disabled)
The input capture register is initialized to H’0000 at a reset and in the standby modes.
Note: When input capture is detected, the FRC value is transferred to the input capture register
even if the input capture flag is already set.
7.2.4 Timer Control Register (TCR) – H’FF90
Bit
Initial value
Read/Write
7
6
5
4
ICIE OCIEB OCIEA OVIE
0
0
0
0
R/W R/W R/W R/W
3
OEB
0
R/W
2
OEA
0
R/W
1
0
CKS1 ^FigC⁷K^-2S0
0
0
R/W R/W
The TCR is an 8-bit readable/writable register that enables and disables output signals and
interrupts, and selects the timer clock source.
The TCR is initialized to H’00 at a reset and in the standby modes.
Bit 7 – Input Capture Interrupt Enable (ICIE): Selects whether to request an input capture
interrupt (ICI) when the input capture flag (ICF) in the timer status/control register (TCSR) is set to
1.
Bit 7
ICIE
0
1
Description
Input capture interrupt request (ICI) is disabled.
Input capture interrupt request (ICI) is enabled.
(Initial value)
Bit 6 – Output Compare Interrupt B Enable (OCIBE): Selects whether to request output
compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer status/control
register (TCSR) is set to 1.
128