HD6473258CP10 Datasheet, PDF (182/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

9.2.6 Serial Control Register (SCR) – H’FFDA
Bit
7
6
5
4
3
TIE RIE
TE
RE
—
Initial value
0
0
0
0
1
Read/Write
R/W R/W R/W R/W —
2
1
0
— CKE1 CKE0
1
0
0
— R/W R/W
The SCR is an 8-bit readable/writable register that enables or disables various SCI functions. It is
initialized to H’0C at a reset and in the standby modes.
Bit 7 – Transmit Interrupt Enable (TIE): This bit enables or disables the transmit-end interrupt
(TXI) requested when the transmit data register empty (TDRE) bit in the serial status register (SSR)
is set to 1.
Bit 7
TIE
0
1
Description
The transmit-end interrupt request (TXI) is disabled.
The transmit-end interrupt request (TXI) is enabled.
(Initial value)
Bit 6 – Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt
(RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR) is
set to 1, and the receive error interrupt (ERI) requested when the overrun error bit (ORER), framing
error bit (FER), or parity error bit (PER) is set to 1.
Bit 6
RIE
0
1
Description
The receive-end interrupt (RXI) request is disabled.
The receive-end interrupt (RXI) request is enabled.
(Initial value)
Bit 5 – Transmit Enable (TE): This bit enables or disables the transmit function. When the
transmit function is enabled, the TxD pin is automatically used for output. When the transmit
function is disabled, the TxD pin can be used as a general-purpose I/O port.
Bit 5
TE Description
0 The transmit function is disabled.
The TxD pin can be used for general-purpose I/O.
1 The transmit function is enabled.
The TxD pin is used for output.
(Initial value)
175