HD6473258CP10 Datasheet, PDF (63/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

• Phenomenon
— H8/300 CPU will malfunction after EEPMOV instruction execution.
• Counter Measures by Software or Circuitry
Please take at least one counter measure from the followings.
— Please use EEPMOV when the destination is in the internal area (e.g. internal RAM).
— When the destination is the external area, please avoid wait state insertion to the bus cycle.
— When the case that wait state(s) is required, please substitute EEPMOV by MOV and other
instructions as follows:
Example
LOOP:MOV.B @R5+, R4H
MOV.B R4H, @R6
ADDS #1, R6
INC R4L
BNE LOOP
3.6 CPU States
The CPU has three states: the program execution state, exception-handling state, and power-down
state. The power-down state is further divided into three modes: the sleep mode, software standby
mode, and hardware standby mode. Figure 3-11 summarizes these states, and figure 3-12 shows a
map of the state transitions.
State
Program execution state
The CPU executes successive program instructions.
Exception-handling state
A transient state triggered by a reset or interrupt. The CPU executes a hardware
sequence that includes loading the program counter from the vector table.
Power-down state
Sleep mode
A state in which some or all of the chip
Software standby mode
functions are stopped to conserve power.
Hardware standby mode
Figure 3-11. Operating States
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