HD6473258CP10 Datasheet, PDF (12/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table 1-1 lists the features of the H8/325 Series.
Table 1-1. Features
Feature
CPU
Memory
16-Bit free-running
timer module
(FRT: 1 channel)
8-Bit timer module
(2 channels)
Description
General register architecture
• Eight 16-bit general registers, or
• Sixteen 8-bit general registers
High speed
• Maximum clock rate: 10 MHz
• Add/subtract: 0.2 µs
• Multiply/divide: 1.4 µs
Concise, streamlined instruction set
• All instructions are 2 or 4 bytes long
• Register-register arithmetic and logic operations
• Register-memory data transfer by MOV instruction
Instruction set features
• Multiply instruction (8 bits × 8 bits)
• Divide instruction (16 bits ÷ 8 bits)
• Bit-accumulator instructions
• Register-indirect specification of bit positions
H8/3257
• ROM: 60 kbytes
• RAM: 2 kbytes
H8/3256
• ROM: 48 kbytes
• RAM: 2 kbytes
H8/325
• ROM: 32 kbytes
• RAM: 1 kbyte
H8/324
• ROM: 24 kbytes
• RAM: 1 kbyte
H8/323
• ROM: 16 kbytes
• RAM: 512 bytes
H8/322
• ROM: 8 kbytes
• RAM: 256 bytes
• One 16-bit free-running counter (also usable for external event counting)
• Two compare outputs
• One capture input
Each channel has:
• One 8-bit up-counter (also usable for external event counting)
• Two time constant registers
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