HD6473258CP10 Datasheet, PDF (274/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

TCSR—Timer Control/Status Register
H’FF91
FRT
Bit
7
6
ICF OCFB
Initial value 0
0
Read/Write R/(W)* R/(W)*
5
4
3
2
OCFA OVF OLVLB OLVLA
0
0
0
0
R/(W)* R/(W)* R/W R/W
1
IEDG
0
R/W
0
CCLRA
0
R/W
Counter Clear A
0 FRC is not cleared.
1 FRC is cleared at compare-match A.
Input Edge Select
0 Falling edge of FTI is valid.
1 Rising edge of FTI is valid.
Output Level A
0 Compare-match A causes 0 output.
1 Compare-match A causes 1 output.
Output Level B
0 Compare-match B causes 0 output.
1 Compare-match B causes 1 output.
Timer Overflow Flag
0 Cleared by reading OVF = 1, then writing 0.
1 Set when FRC changes from H’FFFF to H’0000.
Output Compare Flag A
0 Cleared by reading OCFA = 1, then writing 0.
1 Set when FRC = OCRA.
Output Compare Flag B
0 Cleared by reading OCFB = 1, then writing 0.
1 Set when FRC = OCRB.
Input Capture Flag
0 Cleared by reading ICF = 1, then writing 0.
1 Set when FTI input causes FRC to be copied to ICR.
* Software can write a 0 in bits 7 to 4 to clear the flags, but cannot write a 1 in these bits.
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