HD6473258CP10 Datasheet, PDF (76/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit 2
IRQ2SC
0
0
1
1
Bit 6
IRQ2EG
0
1
0
1
Description
The low level of IRQ2 generates an interrupt request. (Initial state)
The falling edge of IRQ2 generates an interrupt request.
The rising edge of IRQ2 generates an interrupt request.
Bits 5 and 1—IRQ1 Sense Control (IRQ1SC and IRQ1EG): These bits select how the input at
the IRQ1 pin is sensed.
Bit 1
IRQ1SC
0
0
1
1
Bit 5
IRQ1EG
0
1
0
1
Description
The low level of IRQ1 generates an interrupt request. (Initial state)
The falling edge of IRQ1 generates an interrupt request.
The rising edge of IRQ1 generates an interrupt request.
Bits 4 and 0—IRQ0 Sense Control (IRQ0SC and IRQ0EG): These bits select how the input at
the IRQ0 pin is sensed.
Bit 0
IRQ0SC
0
0
1
1
Bit 4
IRQ0EG
0
1
0
1
Description
The low level of IRQ0 generates an interrupt request. (Initial state)
The falling edge of IRQ0 generates an interrupt request.
The rising edge of IRQ0 generates an interrupt request.
(3) IRQ Enable Register (IER)—H’FFC7
Bit
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
Read/Write
—
—
—
—
3
2
1
0
— IRQ2E IRQ1E IRQ0E
1
0
0
0
—
R/W R/W R/W
Bits 0 to 2—IRQ0 to IRQ2 Enable (IRQ0E to IRQ2E): These bits enable or disable the IRQ0,
IRQ1, and IRQ2 interrupts individually.
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