HD6473258CP10 Datasheet, PDF (228/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

The NMI edge bit (NMIEG) in the system control register is originally cleared to 0, selecting the
falling edge. When NMI goes low, the NMI interrupt handling routine sets NMIEG to 1 (selecting
the rising edge), sets SSBY to 1, then executes the SLEEP instruction. The chip enters the software
standby mode. It recovers from the software standby mode on the next rising edge of NMI.
Clock
generator
Ø
NMI
NMIEG
SSBY
Settling time
NMI interrupt handler
NMIEG = 1
SSBY = 1
Software standby mode
(power-down state)
SLEEP
NMI interrupt handler
Figure 12-1. Software Standby Mode NMI Timing (Example)
12.4.4 Notes on Current Dissipation
1. The I/O ports remain in their current states in software standby mode. If a port is in the high
output state, it continues to dissipate power in proportion to the output current.
Fig 12-1
2. When software standby mode is entered under condition (a) or (b) below, current dissipation is
higher (ICC = 100 to 300 µA) than normal in standby mode.
(a) In single-chip mode (mode 3): when software standby mode is entered by executing an
instruction stored in on-chip ROM, after even one instruction not stored in on-chip ROM
has been fetched (e.g. from on-chip RAM).
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