HD6473258CP10 Datasheet, PDF (5/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

3.5.8 Block Data Transfer Instruction .............................................................................. 52
3.6 CPU States ............................................................................................................................ 54
3.6.1 Program Execution State ......................................................................................... 55
3.6.2 Exception-Handling State........................................................................................ 55
3.6.3 Power-Down State ................................................................................................... 56
3.7 Access Timing and Bus Cycle .............................................................................................. 56
3.7.1 Access to On-Chip Memory (RAM and ROM) ...................................................... 56
3.7.2 Access to On-Chip Register Field and External Devices ........................................ 58
Section 4. Exception Handling............................................................................................ 61
4.1 Overview............................................................................................................................... 61
4.2 Reset ..................................................................................................................................... 61
4.2.1 Overview ................................................................................................................. 61
4.2.2 Reset Sequence ........................................................................................................ 61
4.2.3 Disabling of Interrupts after Reset........................................................................... 64
4.3 Interrupts............................................................................................................................... 64
4.3.1 Overview ................................................................................................................. 64
4.3.2 Interrupt-Related Registers...................................................................................... 65
4.3.3 External Interrupts ................................................................................................... 68
4.3.4 Internal Interrupts .................................................................................................... 69
4.3.5 Interrupt Handling ................................................................................................... 70
4.3.6 Interrupt Response Time.......................................................................................... 75
4.4 Note on Stack Handling........................................................................................................ 75
Section 5. I/O Ports ................................................................................................................ 77
5.1 Overview............................................................................................................................... 77
5.2 Port 1..................................................................................................................................... 78
5.3 Port 2..................................................................................................................................... 81
5.4 Port 3..................................................................................................................................... 84
5.5 Port 4..................................................................................................................................... 87
5.6 Port 5..................................................................................................................................... 94
5.7 Port 6..................................................................................................................................... 99
5.8 Port 7..................................................................................................................................... 104
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