HD6473258CP10 Datasheet, PDF (263/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table A-4. Number of Cycles in Each Instruction
Instruction Mnemonic
ADD
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDS
ADDS.W #1/2, Rd
ADDX
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
AND
AND.B #xx:8, Rd
AND.B Rs, Rd
ANDC
ANDC #xx:8, CCR
BAND
BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
Bcc
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
BCLR
BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @Rd
BCLR Rn, @aa:8
Instruction Branch
fetch
addr. read
I
J
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
2
2
Stack
operation
K
Byte data Word data Internal
access access
operation
L
M
N
1
1
2
2
2
2
Note: Blank entries are all zero.
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