HD6473258CP10 Datasheet, PDF (73/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

4.2.3 Disabling of Interrupts after Reset
All interrupts, including NMI, are disabled immediately after a reset. The first program instruction,
located at the address specified at the top of the vector table, is therefore always executed. To
prevent program crashes, this instruction should initialize the stack pointer (example: MOV.W
#xx:16, SP). After execution of this instruction, the NMI interrupt is enabled. Other interrupts
remain disabled until their enable bits are set to 1.
4.3 Interrupts
4.3.1 Overview
There are four input pins for external interrupts (NMI, IRQ0 to IRQ2). There are also 17 internal
interrupts originating on-chip. The features of these interrupts are:
• All internal and external interrupts except NMI can be masked by the I bit in the CCR.
• IRQ0 to IRQ2 can be rising-edge-sensed, falling-edge-sensed, or level-sensed. The type of
sensing can be selected for each interrupt individually. NMI is edge-sensed, and either the rising
or falling edge can be selected.
• Interrupts are individually vectored. The software interrupt-handling routine does not have to
determine what type of interrupt has occurred.
Table 4-2 lists all the interrupts in their order of priority and gives their vector numbers and the
addresses of their entries in the vector table.
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