HD6473258CP10 Datasheet, PDF (134/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

7.2 Register Descriptions
7.2.1 Free-Running Counter (FRC) – H’FF92
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
The FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated
from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0)
of the timer control register (TCR).
When the FRC overflows from H’FFFF to H’0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to 1.
Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is written
or read. See section 7.3, CPU Interface for details.
The FRC is initialized to H’0000 at a reset and in the standby modes. It can also be cleared by
compare-match A.
7.2.2 Output Compare Registers A and B (OCRA and OCRB) – H’FF94 and H’FF96
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
value
Read/ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Write
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output compare
flag (OCFA or OCFB) is set in the timer control/status register (TCSR).
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