HD6473258CP10 Datasheet, PDF (265/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Mnemonic
BSR
BSR d:8
BST
BST #xx:3, Rd
BST #xx:3, @Rd
BST #xx:3, @aa:8
BTST
BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @Rd
BTST Rn, @aa:8
BXOR
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
CMP
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W Rs, Rd
DAA
DAA.B Rd
DAS
DAS.B Rd
DEC
DEC.B Rd
DIVXU DIVXU.B Rs, Rd
EEPMOV EEPMOV
INC
INC.B Rd
JMP
JMP @Rn
JMP @aa:16
JMP @@aa:8
JSR
JSR @Rn
JSR @aa:16
JSR @@aa:8
LDC
LDC #xx:8, CCR
LDC Rs, CCR
MOV
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @Rs, Rd
MOV.B @(d:16,Rs), Rd
Instruction Branch
fetch
addr. read
I
J
2
1
2
2
1
2
2
1
2
2
1
2
2
1
1
1
1
1
1
1
2
1
2
2
2
1
2
2
2
1
1
1
1
1
1
2
Stack
operation
K
1
1
1
1
Byte data
access
L
2
2
1
1
1
1
1
1
2n+2^*1
1
1
Word data Internal
access
operation
M
N
6
1
1
1
Note: Blank entries are all zero.
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