HD6473258CP10 Datasheet, PDF (125/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

6.2.2 Port 3 Data Register (P3DR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
P37
P36
P35
P34
P33
P32
P31
P30
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
When the parallel handshaking interface is used for output (P3DDR = H'FF), P3DR stores the
output data. If port 3 is read, the P3DR data are obtained.
When the parallel handshaking interface is used for input (P3DDR = H'00), P3DR has separate
latches for reading and writing. The data written in P3DR control the MOS input pull-ups. When
P3DR is read, data are obtained from the separate input latches if the input strobe flag (ISF) is set to
1, or directly from the input pins if ISF is cleared to 0.
See Section 5.4, Port 3 for further information.
6.2.3 Handshake Control/Status Register (HCSR)
Bit
7
6
5
4
3
2
1
0
ISF ISIE OSE OSS LTE BSE
—
—
Initial value
0
0
0
0
0
0
1
1
Read/Write
R
R/W R/W R/W R/W R/W
—
—
HCSR is an 8-bit register containing control and status information for parallel handshaking. In the
reset and hardware standby modes, HCSR is initialized to H'03. In the software standby mode it
retains its previous value.
Bit 7—Input Strobe Flag (ISF): Indicates that the input strobe signal (IS) has gone low.
ISF is a read-only bit that is set and cleared by hardware. It is set by strobe input. It is cleared when
the port 3 data register is written or read. (The handshake control/status register must be read first.)
Bit 7
ISF
0
1
Description
To clear ISF, the CPU must read HCSR after ISF has been
set to 1, then read or write the port 3 data register (P3DR).
ISF is set to 1 on the falling edge of IS.
(Initial value)
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