HD6473258CP10 Datasheet, PDF (147/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Ø
Internal compare-
match A signal
FRC
N
H'0000
Figure 7-8. Clearing of FRC by Compare-Match A
7.4.4 Input Capture Timing
(1) Input Capture Timing without Noise Canceler: An internal input capture signal is generated
from the rising or falling edge of the FTI input, as selected by the IEDG bit in the TCSR. Figure 7-
9 shows the usual input capture timing when the rising edge is selected (IEDG = 1).
Fig 7-8
Ø
Input at FTI pin
Internal input
capture signal
Figure 7-9. Input Capture Timing (Usual Case)
If the upper byte of the ICR is being read when the internal input capture signal should be
generated, the internal input capture signal is delayed by one state. Figure 7-10 shows the timing
for this case.
Fig 7-9
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