HD6473258CP10 Datasheet, PDF (78/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

4.3.4 Internal Interrupts
Seventeen internal interrupts can be requested by the on-chip supporting modules. All of them are
masked when the I bit in the CCR is set. In addition, they can all be enabled or disabled by bits in
the control registers of the on-chip supporting modules. When one of these interrupts is accepted,
the I bit is set to 1 to mask further interrupts (except NMI).
Power can be conserved by waiting for an internal interrupt in sleep mode, in which the CPU halts
but the on-chip supporting modules continue to run. When the interrupt arrives, the CPU returns to
the program-execution state, services the interrupt, then resumes execution of the main program.
See section 12, Power-Down State for further information on the sleep mode.
The input strobe interrupt (ISI) can also be waited for in software standby mode. The chip recovers
from software standby mode when an input strobe interrupt is requested.
The internal interrupt signals received by the interrupt controller are generated from flag bits in the
registers of the on-chip supporting modules. The interrupt controller does not reset these flag bits
when accepting the interrupt.
For the vector numbers and priority order of these interrupts, see table 4-2.
Note: When disabling internal interrupts, note the following points.
1. Set the interrupt mask (I) to 1 before disabling an internal interrupt or clearing its interrupt flag.
2. If an instruction that disables or clears an internal interrupt is executed while the interrupt mask
(I) is cleared to 0, and the interrupt is requested during execution of the instruction, the CPU
resolves this conflict as follows:
ΠIf one or more other interrupts are also requested, the other interrupt with the highest priority
is served.
 If no other interrupt is requested, the CPU branches to the reset address.
Example: A sample program for disabling the output compare A interrupt is shown below. The
OCIAE bit in the TCR should be cleared only when I = 1, as in this example.
ORC
BCLR
ANDC
#80, CCR
#5, @TCR
#7F, CCR
; Set I bit
; Disable output compare A interrupt
; Clear I bit
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