HD6473258CP10 Datasheet, PDF (155/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

OCRA or OCRB lower byte write cycle
T1
T2
T3
Ø
Internal address bus
OCR address
Internal write signal
FRC
N
N+1
OCRA or OCRB
Compare-match
A or B signal
N
M
Write data
Inhibited
Figure 7-19. Contention between OCR Write and Compare-Match
(4) Incrementation Caused by Changing of Internal Clock Source: When an internal clock
source is changed, the changeover may cause the FRC to increment. This depends on the time at
which the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 7_F-_ig5._7-19
The pulse that increments the FRC is generated at the falling edge of the internal clock source. If
clock sources are changed when the old source is high and the new source is low, as in case No. 3
in table 7-5, the changeover generates a falling edge that triggers the FRC increment clock pulse.
Switching between an internal and external clock source can also cause the FRC to increment.
147