HD6473258CP10 Datasheet, PDF (137/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit 6
OCIBE
0
1
Description
Output compare interrupt request B (OCIB) is disabled.
Output compare interrupt request B (OCIB) is enabled.
(Initial value)
Bit 5 – Output Compare Interrupt A Enable (OCIAE): Selects whether to request output
compare interrupt A (OCIA) when output compare flag A (OCFA) in the timer status/control
register (TCSR) is set to 1.
Bit 5
OCIAE
0
1
Description
Output compare interrupt request A (OCIA) is disabled.
Output compare interrupt request A (OCIA) is enabled.
(Initial value)
Bit 4 – Timer overflow Interrupt Enable (OVIE): Selects whether to request a free-running
timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in the timer status/control
register (TCSR) is set to 1.
Bit 4
OVIE
0
1
Description
Timer overflow interrupt request (FOVI) is disabled.
Timer overflow interrupt request (FOVI) is enabled.
(Initial value)
Bit 3 – Output Enable B (OEB): Enables or disables output of the output compare B signal
(FTOB). If output compare B is enabled, the FTOB pin is driven to the level selected by OLVLB in
the timer status/control register (TCSR) whenever the FRC value matches the value in output
compare register B (OCRB).
Bit 3
OEB
0
1
Description
Output compare B output is disabled.
Output compare B output is enabled.
(Initial value)
Bit 2 – Output Enable A (OEA): Enables or disables output of the output compare A signal
(FTOA). If output compare A is enabled, the FTOA pin is driven to the level selected by OLVLA in
the timer status/control register (TCSR) whenever the FRC value matches the value in output
compare register A (OCRA).
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