HD6473258CP10 Datasheet, PDF (146/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Ø
FTCI
Figure 7-6. Minimum External Clock Pulse Width
7.4.2 Output Compare Timing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or OLVLB)
in the TCSR is output at the output compare pin (FTOA or FTOB). Figure 7-7 shows the timing of
this operation for compare-match A.
Fig 7-6
Ø
FRC
N
N+1
N
N+1
OCRA
N
Internal compare-
match A signal
OLVLA
N
Clear *
FTOA
* Cleared by software
Figure 7-7. Timing of Output Compare A
7.4.3 FRC Clear Timing
If the CCLRA bit in the TCSR is set to 1, the FRC is cleared when compare-match A occurs.
Figure 7-8 shows the timing of this operation.
Fig 7-7
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