HD6473258CP10 Datasheet, PDF (262/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

A.3 Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution.
Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A-4 indicates
the number of cycles of each type occurring in each instruction. The total number of states required
for execution of an instruction can be calculated from these two tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
From table A-4: I = L = 2, J = K = M = N= 0
From table A-3: SI = 8, SL = 3
Number of states required for execution: 2 × 8 + 2 × 3 =22
2. JSR @@30
From table A-4: I = 2, J = K = 1, L = M = N = 0
From table A-3: SI = SJ = SK = 8
Number of states required for execution: 2 × 8 + 1 × 8 + 1 × 8 = 32
Table A-3. Number of States Taken by Each Cycle in Instruction Execution
Execution status
(instruction cycle)
Instruction fetch SI
Branch address read SJ
Stack operation SK
Byte data access SL
Word data access SM
Internal operation SN
Access location
On-chip memory On-chip reg. field
External memory
6
2
3
6
2
6 + 2m
3 + m (note 2)
6 + 2m
Notes: 1. m: Number of wait states inserted in access to external device.
2. The byte data access cycle to an external device by the MOVFPE and MOVTPE
instructions requires 9 to 16 states since it is synchronized with the E clock. See
section 13, E-Clock Interface for timing details.
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