HD6473258CP10 Datasheet, PDF (186/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

9.2.8 Bit Rate Register (BRR) – H’FFD9
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W
The BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in the SMR, determines
the baud rate output by the baud rate generator.
The BRR is initialized to H’FF (the slowest rate) at a reset and in the standby modes.
Tables 9-3 and 9-4 show examples of BRR (N) and CKS (n) settings for commonly used bit rates.
Table 9-3. Examples of BRR Settings in Asynchronous Mode (1)
Bit
rate n
110 1
150 0
300 0
600 0
1200 0
2400 0
4800 —
9600 —
19200 —
31250 —
38400 —
2
Error
N (%) n
70 +0.03 1
207 +0.16 0
103 +0.16 0
51 +0.16 0
25 +0.16 0
12 +0.16 0
—— 0
—— 0
—— 0
—— —
—— 0
XTAL Frequency (MHz)
2.4576
4
Error
N (%) n N
86 +0.31 1 141
255 0
1 103
127 0
0 207
63 0
0 103
31 0
0 51
15 0
0 25
70
0 12
30
——
10
——
—— 0 1
00
——
Error
(%) n
+0.03 1
+0.16 1
+0.16 0
+0.16 0
+0.16 0
+0.16 0
+0.16 0
——
——
0
—
——
4.194304
Error
N (%)
148 –0.04
108 +0.21
217 +0.21
108 +0.21
54 –0.70
26 +1.14
13 –2.48
——
——
——
——
179