HD6473258CP10 Datasheet, PDF (154/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

FRC lower byte write cycle
T1
T2
T3
Ø
Internal address bus
Internal write signal
FRC address
FRC clock pulse
FRC
N
M
Write data
Figure 7-18. FRC Write-Increment Contention
(3) Contention between OCR Write and Compare-Match: If a compare-match occurs during
the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes precedence and
the compare-match signal is inhibited.
Fig 7-18
Figure 7-19 shows this type of contention.
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