HD6473258CP10 Datasheet, PDF (7/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

7.4.6 Setting of FRC Overflow Flag (OVF)..................................................................... 141
7.5 Interrupts............................................................................................................................... 142
7.6 Noise Canceler...................................................................................................................... 142
7.7 Sample Application............................................................................................................... 144
7.8 Application Notes ................................................................................................................. 145
Section 8. 8-Bit Timers .........................................................................................................151
8.1 Overview............................................................................................................................... 151
8.1.1 Features.................................................................................................................... 151
8.1.2 Block Diagram......................................................................................................... 151
8.1.3 Input and Output Pins .............................................................................................. 152
8.1.4 Register Configuration ............................................................................................ 153
8.2 Register Descriptions............................................................................................................ 153
8.2.1 Timer Counter (TCNT) – H’FFC8 (TMR0), H’FFD0 (TMR1) .............................. 153
8.2.2 Time Constant Registers A and B (TCORA and TCORB) –
H’FFCA and H’FFCB (TMR0), H’FFD2 and H’FFD3 (TMR1)............................ 154
8.2.3 Timer Control Register (TCR) – H’FFC8 (TMR0), H’FFD0 (TMR1) ................... 154
8.2.4 Timer Control/Status Register (TCSR) – H’FFC9 (TMR0), H’FFD1 (TMR1)...... 156
8.3 Operation .............................................................................................................................. 158
8.3.1 TCNT Incrementation Timing................................................................................. 158
8.3.2 Compare Match Timing........................................................................................... 159
8.3.3 External Reset of TCNT .......................................................................................... 161
8.3.4 Setting of TCSR Overflow Flag .............................................................................. 162
8.4 Interrupts............................................................................................................................... 163
8.5 Sample Application............................................................................................................... 163
8.6 Application Notes ................................................................................................................. 164
Section 9. Serial Communication Interface .....................................................................169
9.1 Overview............................................................................................................................... 169
9.1.1 Features.................................................................................................................... 169
9.1.2 Block Diagram......................................................................................................... 170
9.1.3 Input and Output Pins .............................................................................................. 170
9.1.4 Register Configuration ............................................................................................ 171
9.2 Register Descriptions............................................................................................................ 171
9.2.1 Receive Shift Register (RSR) .................................................................................. 171
9.2.2 Receive Data Register (RDR) – H’FFDD ............................................................... 172
9.2.3 Transmit Shift Register (TSR)................................................................................. 172
9.2.4 Transmit Data Register (TDR) – H’FFDB .............................................................. 172
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