HD6473258CP10 Datasheet, PDF (266/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Table A-4. Number of Cycles in Each Instruction (cont.)
Instruction Mnemonic
MOV
MOV.B @Rs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @–Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd)
MOV.W Rs, @–Rd
MOV.W Rs, @aa:16
MOVFPE MOVFPE @aa:16, Rd
MOVTPE MOVTPE.Rs, @aa:16
MULXU MULXU.Rs, Rd
NEG
NEG.B Rd
NOP
NOP
NOT
NOT.B Rd
OR
OR.B #xx:8, Rd
OR.B Rs, Rd
ORC
ORC #xx:8, CCR
ROTL
ROTL.B Rd
ROTR
ROTR.B Rd
ROTXL ROTXL.B Rd
ROTXR ROTXR.B Rd
RTE
RTE
RTS
RTS
Instruction Branch
fetch
addr. read
I
J
1
1
2
1
2
1
1
2
2
1
1
2
1
2
1
2
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
2
2
Stack
operation
K
2
1
Byte data
access
L
1
1
1
1
1
1
1
1
1^*2
1^*2
Word data Internal
access
operation
M
N
1
1
1
1
1
1
1
1
1
1
1
1
6
1
1
Note: Blank entries are all zero.
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