HD6473258CP10 Datasheet, PDF (140/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

Bit 4
OVF
0
1
Description
To clear OVF, the CPU must read OVF after
(Initial value)
it has been set to 1, then write a 0 in this bit.
This bit is set to 1 when FRC changes from H’FFFF to H’0000.
Bit 3 – Output Level B (OLVLB): Selects the logic level output at the FTOB pin when the FRC
and OCRB values match.
Bit 3
OLVLB
0
1
Description
A 0 logic level is output for compare-match B.
A 1 logic level is output for compare-match B.
(Initial value)
Bit 2 – Output Level A (OLVLA): Selects the logic level output at the FTOA pin when the FRC
and OCRA values match.
Bit 2
OLVLA
0
1
Description
A 0 logic level is output for compare-match A.
A 1 logic level is output for compare-match A.
(Initial value)
Bit 1 – Input Edge Select (IEDG): Selects the rising or falling edge of the input capture signal
(FTI).
Bit 1
IEDG
0
1
Description
FRC contents are transferred to ICR on the falling edge of FTI. (Initial value)
FRC contents are transferred to ICR on the rising edge of FTI.
Bit 0 – Counter Clear A (CCLRA): Selects whether to clear the FRC at compare-match A (when
the FRC and OCRA values match).
Bit 0
CCLRA
0
1
Description
The FRC is not cleared.
The FRC is cleared at compare-match A.
(Initial value)
132