HD6473258CP10 Datasheet, PDF (160/301 Pages) Renesas Technology Corp – Hitachi Single-Chip Microcomputer

8.1.4 Register Configuration
Table 8-2 lists the registers of the 8-bit timer module. Each channel has an independent set of
registers.
Table 8-2. 8-Bit Timer Registers
Name
Timer control register
Timer control/status register
Timer constant register A
Timer constant register B
Timer counter
Abbreviation
TCR
TCSR
TCORA
TCORB
TCNT
R/W
R/W
R/(W)*
R/W
R/W
R/W
Initial value
H’00
H’10
H’FF
H’FF
H’00
Address
TMR0
H’FFC8
H’FFC9
H’FFCA
H’FFCB
H’FFCC
TMR1
H’FFD0
H’FFD1
H’FFD2
H’FFD3
H’FFD4
* Software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits.
8.2 Register Descriptions
8.2.1 Timer Counter (TCNT) – H’FFC8 (TMR0), H’FFD0 (TMR1)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W
Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from one of
four clock sources. The clock source is selected by clock select bits 2 to 0 (CKS2 to CKS0) of the
timer control register (TCR). The CPU can always read or write the timer counter.
The timer counter can be cleared by an external reset input or by an internal compare-match signal
generated at a compare-match event. Counter clear bits 1 and 0 (CCLR1 and CCLR0) of the timer
control register select the method of clearing.
When a timer counter overflows from H’FF to H’00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to 1.
The timer counters are initialized to H’00 at a reset and in the standby modes.
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