M30222 Datasheet, PDF (9/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Operation of Functional Blocks
The M30222 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation
circuit, A-D converter, LCD, and I/O ports. The following explains each unit.
Memory
Figure 1.5 is a memory map of the M30222 group. The linear address space of 1M bytes extends from
address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30222FG-XXXFP, there
is 256K bytes of internal ROM from C000016 to FFFFF16. The vector table for fixed interrupts such as the
reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored
here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal
register (INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30222FG-XXXFP, 20K bytes of internal RAM is mapped
to the space from 0040016 to 053FF16. In addition to storing data, the RAM also stores the stack used
when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Tables 1.5 to 1.9 show the
location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and
cannot be used for other purposes.
0000016
SFR area
For details, see Tables
0040016
1.5-1.9
XXXXX16
Internal RAM area
Internal reserved
area
Type No.
Address XXXXX16 Address YYYYY 16
M30222MG/FG/GP
053FF16
C000016
Fig. 1.5. Memory Map
D000016
YYYYY16
FFFFF16
Internal ROM area
FFE0016
Special page
vector table
FFFDC16
FFFFF16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
1-10