M30222 Datasheet, PDF (197/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register
The status register shows the operating state of the flash memory and whether erase operations and
programs ended successfully or in error. It can be read in the following ways.
(1) By reading an arbitrary address from the user ROM area after writing the read status register command (7016)
(2) By reading an arbitrary address from the user ROM area in the period from when the program starts or erase operation starts
to when the read array command (FF16).
Also, the status register can be cleared by writing the clear status register command (5016). After a reset, the
status register is set to "8016".
Table 1.76. Definition of each bit in status register
Each SRD bit
Status name
SR7 (bit 7)
SR6 (bit 6)
SR5 (bit 5)
SR4 (bit 4)
SR3 (bit 3)
SR2 (bit 2)
SR1 (bit 1)
SR0 (bit 0)
Write state machine (WSM) status
Reserved
Erase status
Program status
Reserved
Over write back status
Over erase status
Reserved
Definition
1
0
Ready
_
Terminated in error
Terminated in error
_
Terminated in error
Terminated in error
_
Busy
_
Terminated normally
Terminated normally
_
Terminated normally
Terminated normally
_
Each bit in this register is explained below.
Sequencer status (SR7)
After power-on, the sequencer status is set to 1 (ready). The sequencer status indicates the operating status of
the device. This status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of
these operations.
Erase status (SR5)
The erase status informs the operating status of erase operation to the CPU. When an erase error occurs, it is set
to 1. The erase status is reset to 0 when cleared.
Program status (SR4)
The program status informs the operating status of write operation to CPU. When a write error occurs, it is set to
1. The program status is reset to 0 when cleared.
When an erase command is in error (which occurs if the command entered after the block erase command (2016)
is not the confirmation command (D016), both the program status and erase status (SR5) are set to 1. When the
program status or erase status = 1, the following commands entered by the command write are not accepted.
Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error):
(1) When the valid command is not entered correctly
(2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase (2016/D016), or
erase all unlocked blocks (A716/D016) is not the D016 or FF16. However, if FF16 is entered, read array is assumed
and the command that has been set up in the first busy cycle is cancelled.
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