M30222 Datasheet, PDF (111/237 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Specifications in this manual are tentative and subject to change
MITSUBISHI MICROCOMPUTERS
M30222 Group
Rev. G
Serial Communications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
When reset
X0000000 2
Bit
symbol
Bit name
U0IRS UART0 transmit
interrupt cause select bit
Function
(During clock synchronous
serial I/O mode)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Function
(During UART mode)
RW
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous
receive mode enable bit
U1RRM UART1 continuous
receive mode enable bit
CLKMD0 CLK/CLKS select bit 0
CLKMD1 CLK/CLKS select
bit 1 (Note)
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Invalid
Invalid
Invalid
Must always be “0”
RCSP Separate CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Nothing is assigned.
Write "0" when writing to this bit. If read, the value is indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A8 16) = “0”.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
037716
When reset
0016
Bit
symbol
Bit name
IICM I²C mode selection bit
ABC
Arbitration lost detecting
flag control bit
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
0 : Normal mode
1 : I²C mode
Must always be “0”
0 : Update per bit
1 : Update per byte
Must always be “0”
RW
BBS Bus busy flag
0 : STOP condition detected Must always be “0”
1 : START condition detected
(Note 1)
LSYN SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Must always be “0”
ABSCS ^{Bus collision detect}
sampling
clock select bit
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ACSE
Auto clear function
select bit of transmit
enable bit
Must always be “0”
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
SSS
Transmit start condition
select bit
Must always be “0”
0 : Ordinary
1 : Falling edge of RxD2
SDDS
SDA digital delay select
bit (Note 2, 3)
0 : Analog delay output is
selected
1 : Digital delay output is
selected (Must always
be "0" when not using
I²C mode)
Must always be "0"
Note 1: Nothing but "0" may be written.
Note 2: When not in I ²C mode, do not set this bit by writing a "1". during normal mode, fix it to "0". When this
bit - "0" , UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA
digital delay setup bits) are initialized to "000", with the analog delay circuit selected. Also, when SDDS
= "0", do not read or write to U2SMR3 register.
Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected
only the digital delay value is effective.
Fig. 1.85. Serial I/O-related registers (5)
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